Field of the Invention
The present invention relates to a redundancy circuit for semiconductor memories having word lines organized in segments. When a word line is defective in a segment, a redundant word line in the same or in a different segment can be activated by virtue of inter-segment redundancy by a segment select signal and through fuse sets assigned to the respective segments.
The word lines of semiconductor memories are usually organized in segments. If so-called inter-segment redundancy is provided, it is possible, given the occurrence of a defective word line, to use redundant word lines both from the same segment in which the defective word line is present and from neighboring segments in order to replace the defective word line.
A problem that arises in the case of inter-segment redundancy is that, if appropriate, the activation of the segment with the defective word line is intended to be prevented and, instead of this, the segment in which the redundant word line is located is intended to be activated. Possibly, this may also be the segment with the defective word line if that segment additionally contains the redundant word line.
In order not to lose any access time, the decoding of the signal which selects the segment to be activated, that is to say the decoding of the segment select signal, must take place very rapidly in such a redundancy circuit for semiconductor memories.
To date, segment select signals which specify the segment with the redundant word line have been generated in existing redundancy circuits by evaluating fuse output signals with the aid of the original row addresses. In other words, an additional logic stage is necessary here in order logically to combine the fuse output signal with the address information.